VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2^m) over Standard Basis(Regular Section)

概要

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To design a high-speed m-bit parallel inversion circuit over GF(2^m), we study two variations for the repetition-operation of the numerical formula, AB^2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(2^8) by using 0.25μm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.
社団法人電子情報通信学会の論文
2002-11-01