50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing(<特集>Special Issue on Superconductive Electronics)
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概要
- 論文の詳細を見る
We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz oper- ation. The chosen current density is 6.5 kA/cm^2 simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.
- 社団法人電子情報通信学会の論文
- 2002-03-01
著者
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Van Duzer
Univ. California Ca Usa
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Van Duzer
Department Of Electrical Engineering And Computer Sciences University Of California
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ZHENG Lizhen
Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory,
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MENG Xiaofan
Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory,
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WHITELEY Stephen
Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory,
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Whiteley Stephen
Department Of Electrical Engineering And Computer Sciences And The Electronics Research Laboratory U
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Van Duzer
Department Of Electrical Engineering And Computer Sciences And The Electronics Research Laboratory U
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Meng Xiaofan
Department Of Electrical Engineering And Computer Sciences And The Electronics Research Laboratory U
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Zheng Lizhen
Department Of Electrical Engineering And Computer Sciences And The Electronics Research Laboratory U
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