Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications(<特集>Special Issue on High-Performance and Low-Power Microprocessors)

概要

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This paper presents the HiperSonic 1, a multistandard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802. 11a- and HIPERLAN/2-based 5GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, dataand instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 milliontransistor solution was implemented in 0.18μm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.
社団法人電子情報通信学会の論文
2002-02-01