A 0.25μm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500MHz

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概要

• 論文の詳細を見る

• This paper describes a wide-frequency-range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25μm CMOS/SIMOX technology. The four ratios of internal clock frequency to external clock frequency this generator supports are 2, 4, 8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 500MHz. At 500MHz, the peak-to-peak jitter is 50ps. The supply voltage is 2V and power dissipation is less than 14mW. At a supply voltage of 2V, the maximum operating frequency of 0.25μm CMOS/SIMOX PLL is 30% higher than that of 0.25μm bulk CMOS PLL.

• 1999-07-25

著者

• Yamakoshi Kimihiro

  Ntt Network Service Systems Laboratories

• SUTOH Hiroki

  NTT Lifestyle and Environmental Technology Laboratories

関連論文

• A 0.25μm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500MHz
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