5.4 GOPS, 81 GB/s Linear Array Architecture DSP(Special Issue on Multimedia, Network, and DRAM LSIs)

概要

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A programmable DSP with linear array architecture for real-time video processing is reported. It achieves a processing rate of 5.4GOPS and 81GB/s memory bandwidth using Dual Sense Amplifier architecture. A low-power-supply pipeline decreases power consumption and a time shared bit-line reduces chip area. It has 4320 processor elements and a 1.1Mbit 3-port memory. The DSP can be applied to HDTV signals with its 75MHz peak I/O rate. Sufficient programmability is provided to execute video format conversion such as image size conversion and Y/C separation, and picture quality improvement such as noise reduction and image enhancement. The chip was fabricated using 0.4μm CMOS triple metal technology with a 15.12mm×14.95mm die. It operates at 50MHz and consumes 0.53W/GOPS at 3.3V[1].
社団法人電子情報通信学会の論文
1998-05-25