Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme (Special Issue on Low-Power LSI Technologies)

概要

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The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is,a 0.35μm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme,a new divided layer bitline architecture was developed. As a result, reduction of SRAM macro size of 3 1% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.
社団法人電子情報通信学会の論文
1996-12-25