Low Power Design Technology for Digital LSIs (Special Issue on Low-Power LSI Technologies)

スポンサーリンク

概要

• 論文の詳細を見る

• Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation P_<at> and stand-by power dissipation P_<st> for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing P_<at> are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.)for reduction of Pat. The last part of the paper focuses on reduction of P_<st>. Reducing both Pat and P_<st> requires that both throughput and active chip areas be either maintained or improved.

• 社団法人電子情報通信学会の論文
• 1996-12-25

著者

• Enomoto Tadayoshi

  The Faculty Of Science And Engineering Chuo University

関連論文

• Low Power Design Technology for Digital LSIs (Special Issue on Low-Power LSI Technologies)

スポンサーリンク