Low-Voltage and Low-Power ULSI Circuit Techniques (Special Section on High Speed and High Density Multi Functional LSI Memories)

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概要

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• Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

• 社団法人電子情報通信学会の論文
• 1994-08-25

著者

• Itoh Kiyoo

  The Central Research Laboratory Hitachi Ltd.

• Aoki Masakazu

  the Central Research Laboratory, Hitachi, Ltd.,

• Aoki Masakazu

  The Central Research Laboratory Hitachi Ltd.

関連論文

• Low-Voltage and Low-Power ULSI Circuit Techniques (Special Section on High Speed and High Density Multi Functional LSI Memories)

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