A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

スポンサーリンク

概要

• 論文の詳細を見る

• A monolithic active equalizer in 2-μm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional -pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.

• 社団法人電子情報通信学会の論文
• 1994-05-25

著者

• Abidi Asad

  Integrated Circuits And Systems Laboratory Electrical Engineering Department University Of Californi

• Pai Patrick

  Integrated Circuits and Systems Laboratory, Electrical Engineering Department, University of Califor

• Pai Patrick

  Integrated Circuits And Systems Laboratory Electrical Engineering Department University Of Californi

関連論文

• A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

スポンサーリンク