Influence of Energy Transport Related Effects on NPN BJT Device Performance and ECL Gate Delay Analysed by 2D Parallel Mixed Level Device/Circuit Simulation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
スポンサーリンク
概要
- 論文の詳細を見る
The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.
- 社団法人電子情報通信学会の論文
- 1994-02-25
著者
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Engl Walter
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.
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Stecher Matthias
the Institut fur Theoretische Elektrotechnik, University of Aachen, Kopernikusstr.
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Meinerzhagen Bernd
the Institut fur Theoretische Elektrotechnik, University of Aachen, Kopernikusstr.
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Bork Ingo
the Institut fur Theoretische Elektrotechnik, University of Aachen, Kopernikusstr.
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Krucken Joachim
the Institut fur Theoretische Elektrotechnik, University of Aachen, Kopernikusstr.
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Maas Peter
the Institut fur Theoretische Elektrotechnik, University of Aachen, Kopernikusstr.
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Meinerzhagen Bernd
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.
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Bork Ingo
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.
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Maas Peter
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.
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Krucken Joachim
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.
-
Stecher Matthias
The Institut Fur Theoretische Elektrotechnik University Of Aachen Kopernikusstr.