A 500Megabyte/s Data-Rate 4.5M DRAM (Special Section on the 1992 VLSI Circuits Symposium)

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概要

• 論文の詳細を見る

• In order to improve system bus bandwidth, a novel, small-swing, synchronous bus, which is based on a block-transferoriented protocol, has been proposed. A 4.5M DRAM that interfaces to the bus directly and provides a 500-megabyte / s data rate has been developed.

• 社団法人電子情報通信学会の論文
• 1993-05-25

著者

• Chan Andy

  Rambus Inc.

• Kushiyama Natsuki

  Toshiba Corporation

• Ohshima Shigeo

  Toshiba Corporation

• Stark Don

  Toshiba Corporation

• Noji Hiroyuki

  Toshiba Microelectronics Corporation

• Sakurai Kiyofumi

  Toshiba Microelectronics Corporation

• Takase Satoru

  Toshiba Corporation

• Furuyama Tohru

  Toshiba Corporation

• Barth RichardM.

  Rambus Inc.

• Dillon John

  Rambus Inc.

• Gasbarro JamesA.

  Rambus Inc.

• Griffin MatthewM.

  Rambus Inc.

• Horowitz Mark

  Rambus Inc.

• Lee ThomasH.

  Rambus Inc.

• Furuyama T

  Toshiba Corp. Kawasaki‐shi Jpn

関連論文

• A 500Megabyte/s Data-Rate 4.5M DRAM (Special Section on the 1992 VLSI Circuits Symposium)

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