A 6ns 1Mb CMOS SRAM with Latched Sense Amplifier (Special Section on the 1992 VLSI Circuits Symposium)

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概要

• 論文の詳細を見る

• This paper describes a 1-Mb (256K×4) CMOS SRAM with 6-ns access time. The SRAM, having a cell size of 3.8μm×7.2μm and a die size of 6.09mm×12.94mm, is fabricated by using 0.5-μm triple-polysilicon and doublemetal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new nMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.

• 社団法人電子情報通信学会の論文
• 1993-05-25

著者

• Ozawa Tadashi

  Sram Design Division Fujitsu Vlsi Limited

• Seki Teruo

  SRAM Design Division, Fujitsu VLSI Limited

• Itoh Eisaku

  SRAM Design Division, Fujitsu VLSI Limited

• Furukawa Chiaki

  SRAM Design Division, Fujitsu VLSI Limited

• Maeno Isamu

  SRAM Design Division, Fujitsu VLSI Limited

• Sano Hiroyuki

  SRAM Design Division, Fujitsu VLSI Limited

• Suzuki Noriyuki

  Process Division, Fujitsu Limited Mie Factory

• Seki Teruo

  Sram Design Division Fujitsu Vlsi Limited

• Maeno Isamu

  Sram Design Division Fujitsu Vlsi Limited

• Itoh Eisaku

  Sram Design Division Fujitsu Vlsi Limited

• Furukawa Chiaki

  Sram Design Division Fujitsu Vlsi Limited

• Sano Hiroyuki

  Sram Design Division Fujitsu Vlsi Limited

• Suzuki Noriyuki

  Process Division Fujitsu Limited Mie Factory

関連論文

• A 6ns 1Mb CMOS SRAM with Latched Sense Amplifier (Special Section on the 1992 VLSI Circuits Symposium)

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