A Low-Power 12b Analog-to-Digital Converter with On-Chip Precision Trimming (Special Section on the 1992 VLSI Circuits Symposium)

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概要

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• The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1-μm CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW.

• 社団法人電子情報通信学会の論文
• 1993-05-25

著者

• Dewit Michiel

  Integrated Systems Laboratory Texas Instruments Incorporated

• Tan Khen-Sang

  Institute of Microelectronics

• Hester Richard

  Department of Electrical Engineering and Computer Engineering, Iowa State University

• Hester Richard

  Department Of Electrical Engineering And Computer Engineering Iowa State University

関連論文

• A Low-Power 12b Analog-to-Digital Converter with On-Chip Precision Trimming (Special Section on the 1992 VLSI Circuits Symposium)

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