On Acceleration of Test Points Selection for Scan-Based BIST(Special Issue on Test and Diagnosis of VLSI)

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概要

• 論文の詳細を見る

• This paper presents an acceleration of test points selection for circuits designed by a full-scan based BIST scheme. In order to accelerate the test points selection based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed techniques and evaluate its efficiency experimentally using large scale circuits(26k-420k gates).

• 社団法人電子情報通信学会の論文
• 1998-07-25

著者

• Nakao Michinobu

  Hitachi Research Laboratory Hitachi Ltd.

• Hatayama Kazumi

  Hitachi Research Laboratory Hitachi Ltd.

• HIGASHI Isao

  General Purpose Computer Division, Hitachi Ltd.

• Higashi I

  General Purpose Computer Division Hitachi Ltd.

関連論文

• On Acceleration of Test Points Selection for Scan-Based BIST(Special Issue on Test and Diagnosis of VLSI)

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