Linking Register-Transfer and Physical Levels of Design (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical design. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

• 社団法人電子情報通信学会の論文
• 1993-09-25

著者

• Ramachandran Champaka

  Ece Department University Of California

• Kurdahi FadiJ.

  ECE Department, University of California

• Gajski DanielD.

  ICS Department, University of California

• Chaiyakul Viraphol

  ICS Department, University of California

• Kurdahi Fadij.

  Ece Department University Of California

• Gajski Danield.

  Ics Department University Of California

• Chaiyakul Viraphol

  Ics Department University Of California

関連論文

• Linking Register-Transfer and Physical Levels of Design (Special Issue on Synthesis and Verification of Hardware Design)

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