REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques (Special Issue on VLSI Testing and Testable Design)

概要

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This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N^2-V.
社団法人電子情報通信学会の論文
1993-07-25