A Concurrent Fault Detection Method for Instruction Level Parallel Processors (Special Issue on VLSI Testing and Testable Design)

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概要

• 論文の詳細を見る

• This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.

• 社団法人電子情報通信学会の論文
• 1993-07-25

著者

• Hanawa Makoto

  Ultra-high-speed Processor Research Department At The Central Research Laboratory(hcrl) Hitachi Ltd.

• Pawlovsky AlbertoPalacios

  Ultra-High-Speed Processor Research Department at the Central Research Laboratory(HCRL), Hitachi, Lt

• Pawlovsky Albertopalacios

  Ultra-high-speed Processor Research Department At The Central Research Laboratory(hcrl) Hitachi Ltd.

関連論文

• A Concurrent Fault Detection Method for Instruction Level Parallel Processors (Special Issue on VLSI Testing and Testable Design)

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