A New Charge Pump PLL with Reduced Jitter

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概要

• 論文の詳細を見る

• A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 μm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

• 社団法人電子情報通信学会の論文
• 2001-06-01

著者

• Choi W‐y

  Yonsei Univ. Seoul Kor

• Kim Y‐g

  Yonsei Univ. Seoul Kor

• Lee Myoung-su

  Samsung Electronics

• Choi Woo-young

  The Department Of Electrical And Electronic Eng Yonsei University

• KIM Yu-Gun

  the Department of Electrical and Electronic Engineering, Yonsei University

• Kim Yu-gun

  The Department Of Electrical And Electronic Eng Yonsei University

• Choi Woo-young

  The Department Of Electrical And Electronic Engineering Yonsei University

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• A New Charge Pump PLL with Reduced Jitter
• Novel 622 Mb/s Burst-Mode Clock and Data Recovery Circuits with Muxed Oscillators(Communication Devices/Circuits)

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