Performance Analysis of a Symbol Timing Recovery System for VDSL Transmission

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, we describe statistical properties of timing jitter of symbol timing recovery circuit for carrierless amplitude/phase modulation(CAP)-based very high-rate digital subscriber line(VDSL)system. Analytical expressions of the timing jitter for envelope-based timing recovery system, such as squarer-based timing recovery(S-TR) and absolute-value-based timing recovery(A-TR)schemes, are derived in the presence of additive white gaussian noise(AWGN)or far-end crosstalk(FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5nsec and the acquisition time of 20msec.

• 社団法人電子情報通信学会の論文
• 2001-04-01

著者

• Kim Do-hoon

  Lg Electronics Co. Ltd.

• IM Gi-Hong

  the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology

• Im Gi-hong

  The Department Of Electronic And Electrical Engineering Pohang University Of Science And Technology

関連論文

• Performance Analysis of a Symbol Timing Recovery System for VDSL Transmission

スポンサーリンク