A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems

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概要

• 論文の詳細を見る

• We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.

• 社団法人電子情報通信学会の論文
• 1999-08-25

著者

• Suzuki Yoshifumi

  Ntt Wireless Systems Laboratories

• Suzuki Y

  Kanagawa Inst. Technol. Atsugi‐shi Jpn

• TAKAO Toshiaki

  NTT Wireless Systems Laboratories

• SHIRATO Tadashi

  NTT Advanced Technology Corporation

• Takao T

  Ntt Wireless Systems Laboratories

• Shirato T

  Ntt Advanced Technology Corporation

関連論文

• A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems
• A New Bit Timing Recovery Scheme for High Bit Rate Wireless Access (Special Section on Mutli-dimensional Mobile Information Network)
• Feasibility Study of Variable Multi-Level QAM Modem for Wireless ATM Networks (Special Issue on Advanced Adaptive Radio Communication Technologies)
• A Digitized Group Modulator Using Simple Fractional Sampling for Multi-Carrier TDMA Radio Systems
• A Digitized FH-Group Modem for Adaptive FH and Multi-Carrier Radio Systems (Special Issue on Advanced Adaptive Radio Communication Technologies)

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