On Traffic Burstiness and Priority Assignment for the Real-Time Connections in a Regulated ATM Network (Special Issue on Distributed Processing for Controlling Telecommunications Systems)

概要

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From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.
社団法人電子情報通信学会の論文
1999-06-25