A High-Speed ATM Switch with Input and Cross-Point Buffers

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概要

• 論文の詳細を見る

• This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

• 社団法人電子情報通信学会の論文
• 1993-03-25

著者

• YAMANAKA Naoaki

  NTT Transmission Systems Laboratories

• Doi Yukihiro

  Ntt Telecommunication Switching Laboratories

• Yamanaka Naoaki

  Ntt Telecommunication Switching Laboratories

関連論文

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• Performance Limitation of Leaky Bucket Algorithm for Usage Parameter Control and Bandwidth Allocation Methods
• A High-Speed ATM Switch with Input and Cross-Point Buffers

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