Hardware Algorithm Optimization Using Bach C(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)

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概要

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• The Bach compiler is a behavioral synthesis tool, which synthesizes RT-level circuits from behavioral descriptions written in the Bach C language. It shortens the design period of LSI and helps designers concentrate on algorithm design and refinement. In this paper, we propose methods for optimizing the area and performance of algorithms described in Bach C. In our experiments, we optimized a Viterbi decoder algorithm using our proposed methods and synthesized the circuit using the Bach compiler. The conclusion is that the circuit produced using Bach is both smaller and faster than the hand-coded register transfer level (RTL) design. This proves that the Bach compiler produces high-quality results and the Bach C language is effective for describing the behavior of hardware at a high-level.

• 社団法人電子情報通信学会の論文
• 2002-04-01

著者

• Okada Kazuhisa

  Design Technology Development Laboratories Integrated Circuits Development Group Sharp Corporation

• Yamada A

  Design Technology Development Laboratories Integrated Circuits Development Group Sharp Corporation

• Kambe Takashi

  Design Technology Development Laboratories Integrated Circuits Development Group Sharp Corporation

• YAMADA Akihisa

  Design Technology Development Laboratories, Integrated Circuits Development Group, Sharp Corporation

• Yamada Akihisa

  Design Technology Development Laboratories Integrated Circuits Development Group Sharp Corporation

関連論文

• Hardware Algorithm Optimization Using Bach C(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)

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