A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention

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概要

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• A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35μm 2P4M CMOS process with 3.3V supply. Experimental results show that the circuit avoids false locking.

• 2002-02-01

著者

• Yoo Changsik

  Dram Team 3 Memory Division Samsung Electronics Co. Ltd.

• PARK Sungkyung

  School of Electrical Engineering, Seoul National University

• PARK Sin

  Information and Communications University

関連論文

• A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention

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