A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage(Special Section on Analog Circuit Techniques and Related Topics)

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概要

• 論文の詳細を見る

• Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8μm digital CMOS process.The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications.This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while function at very high sampling rate.The circuit achieved -61dB THD for a 1.42V_<p-p> 10MHz input signal at a 103MHz sampling rate and -55.9dB THD for a 1.22V_<p-p> 20MHz at a 101MHz sampling rate.

• 社団法人電子情報通信学会の論文
• 2000-02-25

著者

• Hadidi Khayrollah

  The Electrical Engineering Department Urmia University

• MATSUMOTO Takashi

  the Department of Electrical, Electronics and Computer Engineering, Waseda University

• SASAKI Masahiro

  the Department of Electrical, Electronics Computer Engineering, Waseda University

• WATANABE Tadatoshi

  the Department of Electrical, Electronics Computer Engineering, Waseda University

• MURAMATSU Daigo

  the Department of Electrical, Electronics Computer Engineering, Waseda University

• Watanabe Tadatoshi

  The Department Of Electrical Electronics Computer Engineering Waseda University

• Muramatsu Daigo

  The Department Of Electrical Electronics Computer Engineering Waseda University

• Sasaki Masahiro

  The Department Of Electrical Electronics Computer Engineering Waseda University

• Matsumoto Takashi

  The Department Of Electrical Electronics And Computer Engineering Waseda University

• Matsumoto Takashi

  The Department Of Electrical Electronics Computer Engineering Waseda University

関連論文

• A Hierarchical Bayesian Approach to Regularization Problems with Multiple Hyperparameters(Special Section on Digital Signal Processing)
• A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage(Special Section on Analog Circuit Techniques and Related Topics)

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