Complete Diagnosis Patterns for Wiring Interconnects

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概要

• 論文の詳細を見る

• It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of multiple interconnect faults.

• 社団法人電子情報通信学会の論文
• 1998-04-25

著者

• Lee Gueesang

  The Author Is With Department Of Computer Science Chonnam National University

• Park Sungju

  The Author Is With Department Of Computer Science & Engineering Hanyang University

関連論文

• Complete Diagnosis Patterns for Wiring Interconnects

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