FFT-Based Implementation of Sampling Rate Conversion with a Small Number of Delays (Special Section on Digital Signal Processing)
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概要
- 論文の詳細を見る
Block delay caused by using fast Fourier transform (FFT), and computational complexity in sampling rate conversion system are considered in this paper. The relationship between the number of block delays and the computational complexity is investigated. The proposed method can avoid the redundant operations of sampling rate conversion completely and moreover provide a good trade-off between the number of block delays and the computational complexity. As a result, it is shown that with the proposed method, the sampling rate conversion can be realized more efficiently under a small number of block delays.
- 社団法人電子情報通信学会の論文
- 1997-08-25
著者
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Muramatsu S
Niigata Univ. Niigata‐shi Jpn
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Muramatsu Shogo
Graduate School Of Engineering Tokyo Metropolitan University
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Muramatsu Shogo
The Faculty Of Technology Tokyo Metropolitan University
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Muramatsu Shogo
Graduate Course Of Electronics Eng. Graduate School Of Eng. Tokyo Metropolitan University
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Kiya Hitoshi
Graduate School Of Engineering Tokyo Metropolitan University
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Kiya Hitoshi
The Department Of Electrical Engineering Graduate School Of Engineering Tokyo Metroporitan Universit
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ZOU Xiaoxia
Graduate School of Engineering, Tokyo Metropolitan University
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Kiya Hitoshi
Graduate Course Of Electronics Eng. Graduate School Of Eng. Tokyo Metropolitan University
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Zou Xiaoxia
Graduate School Of Engineering Tokyo Metropolitan University
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