Current-Mode CMOS-Based Decoder with Redundantly Represented 0 Addend Method for Multiple-Radix Signed-Digit Number (Special Section of Papers Selected from ITC-CSCC'96)

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We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O=[-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of 0. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of 0. Through the parallel connections of these current switches, the same addend signal at the lower digit is transmitted in a higher speed. The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented 0 addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.
社団法人電子情報通信学会の論文
1997-06-25