A 156 Mb/s CMOS Clock Recovery Circuit for Burst-Mode Transmission (Special Section on Analog Circuit Techniques for System-on-Chip Integration)

概要

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This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission such as Fiber-To-The-Home (FTTH). It enables to the handling of asynchronous burst-mode data. Without an external reference clock signal, it can make a quick extraction of clock signal from received data packets using a "gating-timing circuit" and a "burst PLL." The gating-timing circuit employs bit gating for a quick phase response, and the burst PLL employs frame gating for quick frequency adjustment to differences between packets and clock extraction. This circuit has a simple configuration without any external oscillators, which reduces both cost and power. A fabricated 0.5-μm CMOS IC exhibits instantaneous response within one bit for 156 Mb/s asynchronous data packets.
1997-02-25