Power and Timing Optimization for ECL LSIs in Post-Layout Design

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概要

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• In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints is then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating "programmable resistors," which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

• 社団法人電子情報通信学会の論文
• 1996-06-25

著者

• Kitazawa Hitoshi

  Ntt Lsi Laboratories

• Onozawa Akira

  Ntt Lsi Laboratories

• KAWAI Kenji

  NTT LSI Laboratories

関連論文

• A Layout System for Mixed A/D Standard Cell LSI's
• Power and Timing Optimization for ECL LSIs in Post-Layout Design

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