PCHECK: A Delay Analysis Tool for High Performance LSI Design (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1)a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.

• 社団法人電子情報通信学会の論文
• 1996-12-25

著者

• MIKI Yoshio

  The Cancer Institute of Japanese Foundation for Cancer Research (JFCR)

• Miki Yoshio

  The Central Research Laboratory Hitachi Ltd.

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• PCHECK: A Delay Analysis Tool for High Performance LSI Design (Special Section on VLSI Design and CAD Algorithms)

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