Reclocking Controllers for Minimum Execution Time
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概要
- 論文の詳細を見る
In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas : one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths ; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.
- 社団法人電子情報通信学会の論文
- 1995-12-25
著者
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Dutt Nikil
Ics Department University Of California
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Jha Pradip
ICS Department, University of California
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Parameswaran Sri
ECE Department, University of Queensland
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Parameswaran Sri
Ece Department University Of Queensland
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Jha Pradip
Ics Department University Of California