Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems (Special Section on Information Theory and Its Applications)

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概要

• 論文の詳細を見る

• This paper proposes new design methods for single b-bit (b≧2) byte error correcting and double bit error detecting code, called SbEC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This new type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing ones. A code design method using elements from a coset of subfield under addition gives the practical SbEC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the Hamming single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.

• 社団法人電子情報通信学会の論文
• 1993-09-25

著者

• Fujiwara Eiji

  The Faculty Of Engineering Tokyo Institute Of Technology

• Hamada Mitsuru

  the Faculty of Engineering, Tokyo Institute of Technology

• Hamada Mitsuru

  The Faculty Of Engineering Tokyo Institute Of Technology

関連論文

• Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems (Special Section on Information Theory and Its Applications)

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