Fault Analysis on (K+1) Valued PLA Structure Logic Circuits

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概要

• 論文の詳細を見る

• This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.

• 社団法人電子情報通信学会の論文
• 1993-06-25

著者

• Lee C

  National Chiao Tung Univ. Hsinchu Twn

• Wang Hui

  the Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University

• Lee Chung

  the Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University

• Chen Jwu

  the Department of Electrical Engineering, Chung-Hua Polytechnic Institute

• Chen Jwu

  The Department Of Electrical Engineering Chung-hua Polytechnic Institute

• Wang Hui

  The Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung Univers

関連論文

• Fault Analysis on (K+1) Valued PLA Structure Logic Circuits
• Fault Analysis on (K+1) Valued PLA Structure Logic Circuits

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