Placement, Routing, and Compaction Algorithms for Analog Circuits (Special Section on JTC-CSCC '92)

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概要

• 論文の詳細を見る

• The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC bench-mark is shown to demonstrate the performance of the algorithms.

• 社団法人電子情報通信学会の論文
• 1993-06-25

著者

• OHTSUKI Tatsuo

  the School of Science and Engineering, Waseda University

• Ohtsuki Tatsuo

  The School Of Science And Engineering Waseda University

• Awashima Toru

  the School of Science and Engineering, Waseda University

• Asakura Koji

  The School Of Science And Engineering Waseda University

• Awashima Toru

  The Department Of Electronics And Communication Engineering School Of Science And Engineering Waseda

• Mahmoud Imbaby

  School Of Science And Engineering Waseda University

• Mahmoud I.imbaby

  The School Of Science And Engineering Waseda University

関連論文

• Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
• Placement, Routing, and Compaction Algorithms for Analog Circuits (Special Section on JTC-CSCC '92)
• Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method (Special Section on Discrete Mathematics and Its Applications)
• Experimental Appraisal of Linear and Quadratic Objective Functions Effect on Force Directed Method for Analog Placement
• Placement, Routing, and Compaction Algorithms for Analog Circuits (Special Section on JTC-CSCC '92)

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