New Radix-2 to the 4th Power Pipeline FFT Processor(<Special Section>Papers Selected from AP-ASIC 2004)

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概要

• 論文の詳細を見る

• This paper proposes a new modified radix-2^4 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-2^2 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35μm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.

• 社団法人電子情報通信学会の論文
• 2005-08-01

著者

• Oh Jung‐yeol

  Electronics And Telecommunications Res. Inst. Daejeon Kor

• OH Jung-Yeol

  Division of Electronics and Information Engineering, Chonbuk National University

• LIM Myoung-Seob

  Division of Electronics and Information Engineering, Chonbuk National University

関連論文

• New Radix-2 to the 4th Power Pipeline FFT Processor(Papers Selected from AP-ASIC 2004)

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