The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning(Electronic Circuits)
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概要
- 論文の詳細を見る
This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the tradeoff in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35μm CMOS cell library.
- 社団法人電子情報通信学会の論文
- 2005-05-01
著者
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Jen Chein
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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CHEN Hun
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University
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CHANG Tian
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University
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GUO Jiun
Department of Computer Science and Information Engineering, National Chung-Cheng University
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Chen Hun
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University:de
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Guo Jiun
Department Of Computer Science And Information Engineering National Chung-cheng University
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Chang Tian
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University