A Design of Compact PLL with Adaptive Active Loop Filter Circuit(<Special Section>Analog Circuit and Device Technologies)

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概要

• 論文の詳細を見る

• This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15μm-CMOS process. The total chip area of the PLL is reduced to 1/2 of the previous one. The jitter performance is almost equal to conventionally biased PLL.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• DOSHO Shiro

  Corporate System LSI Development Division, Matsushita Electric Industrial Co., Ltd.

• Dosho Shiro

  Corporate Semiconductor Development Division. Matsushita Electric Industrial Co. Ltd.

• Dosho Shiro

  Corporate System Lsi Development Division Matsushita Electric Industrial Co. Ltd.

• Yanagisawa Naoshi

  Corporate Semiconductor Development Division. Matsushita Electric Industrial Co. Ltd.

• Yanagisawa Naoshi

  Corporate System Lsi Development Division Matsushita Electric Industrial Co. Ltd.

• TOYAMA Masaomi

  Corporate System LSI Development Division, Matsushita Electric Industrial Co., Ltd.

• Toyama Masaomi

  Corporate System Lsi Development Division Matsushita Electric Industrial Co. Ltd.

関連論文

• A -90dBc @ 10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit(Analog Circuit and Device Technologies)
• A Design of Compact PLL with Adaptive Active Loop Filter Circuit(Analog Circuit and Device Technologies)
• Development of a CMOS Data Recovery PLL for DVD-ROMx14(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)

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