A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure(Ferroelectric Memory)(<Special Section>New Era of Nonvolatile Memories)

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概要

• 論文の詳細を見る

• This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the onpitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57%, an access time of 85ns and an active current of 12 mA, respectively.

• 社団法人電子情報通信学会の論文
• 2004-10-01

著者

• Kim Jung-hyun

  The School Of Electronic And Electrical Engineering Kyungpook National University

• CHUNG Yeonbae

  the School of Electronic and Electrical Engineering, Kyungpook National University

• YOON Jae-Eun

  the School of Electronic and Electrical Engineering, Kyungpook National University

• Yoon Jae-eun

  The School Of Electronic And Electrical Engineering Kyungpook National University

• Chung Yeonbae

  The School Of Electronic And Electrical Engineering Kyungpook National University

関連論文

• A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure(Ferroelectric Memory)(New Era of Nonvolatile Memories)

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