Low Complexity Multiplexer-Based Parallel Multiplier of GF(2^m)(Computer System Element)

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概要

• 論文の詳細を見る

• Two operations, polynomial multiplication and modular reduction, are newly induced by the properties of the modified Booth's algorithm and irreducible all one polynomials, respectively. A new and effective methodology is hereby proposed for computing multiplication over a class of fields GF(2^m) using the two operations. Then a low complexity multiplexer-based multiplier is presented based on the aforementioned methodology. Our multiplier consists of m 2-input AND gates, an (m^2 +3m-4)/2 2-input XOR gates, and m(m - l)/2 4 × 1 multiplexers. For the detailed estimation of the complexity of our multiplier, we will expand this argument into the transistor count, using a standard CMOS VLSI realization. The compared results show that our work is advantageous in terms of circuit complexity and requires less delay time compared to previously reported multipliers. Moreover, our architecture is very regular modular and therefore, well-suited for VLSI implementation.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Kim Heung-soo

  Department Of Electronics Engineering Inha University

• Byun Gi-young

  School Of Information Communications & Electronics Engineering Catholic University

• Kim H‐s

  Cheju National Univ. Jeju Kor

関連論文

• Low Complexity Multiplexer-Based Parallel Multiplier of GF(2^m)(Computer System Element)
• Low Complexity Multiplexer-Based Parallel Multiplier of GF(2^m)

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