A High-Performance Tree-Block Pipelining Architecture for Separable 2-D Inverse Discrete Wavelet Transform(<Special Issue> Development of Advanced Computer Systems)

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概要

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• In this paper, a high-performance pipelining architecture for 2-D inverse discrete wavelet transform (IDWT) is proposed. We use a tree-block pipeline-scheduling scheme to increase computation performance and reduce temporary buffers The scheme divides the input subbands into several wavelet blocks and processes these blocks one by one, so the size of buffers for storing temporal subbands is greatly reduced. After scheduling the data flow, we fold the computations of all wavelet blocks into the same low-pass and high-pass filters to achieve higher hardware utilization and minimize hardware cost, and pipeline these two filters efficiently to reach higher throughput rate For the computations of N×N-sample 2-D IDWT with filter length of size K, our architecture takes at most (2/3) N^2 cycles and requires 2N (K-2) registers. In addition, each filter is designed regularly and modularly, so it is easily scalable for different filter lengths and different levels. Because of its small storage, regularity, and high performance, the architecture can be applied to time-critical image decompression

• 社団法人電子情報通信学会の論文
• 2003-10-01

著者

• SHIAU Yeu-Horng

  Department of Electrical Engineering National Cheng Kung University Tainan

• Jou Jer

  Department Of Electrical Engineering National Cheng Kung University

• Shiau Yeu-horng

  Department Of Electrical Engineering National Cheng Kung University

関連論文

• Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme(VLSI Systems)
• A High-Performance Tree-Block Pipelining Architecture for Separable 2-D Inverse Discrete Wavelet Transform( Development of Advanced Computer Systems)

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