A New Application-Specific PLD Architecture(<Special Section>Papers Selected from ITC-CSCC 2004)

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概要

• 論文の詳細を見る

• A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.

• 社団法人電子情報通信学会の論文
• 2005-06-01

著者

• Lee Jae-jin

  School Of Electrical And Computer Engineering Chungbuk National University

• SONG Gi-Yong

  School of Electrical and Computer Engineering, Chungbuk National University

• Song Gi-yong

  School Of Electrical And Computer Engineering Chungbuk National University

関連論文

• A New Application-Specific PLD Architecture(Papers Selected from ITC-CSCC 2004)

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