Symbolic Computation of NF of Transistor Circuits(Nonlinear Problems)

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概要

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• A novel method is presented to the symbolic computation of Noise Figure (NF) of transistor circuits. Several computationally efficient macromodels of BJTs and MOSFETs by using nullors, are introduced. To demonstrate the suitability of the proposed method, the fully-symbolic expression of NF of a CMOS current-mirror is computed, and the total output noise-voltage is compared with HSPICE simulations. The calculated NF and the simulated noise are in good agreement. Finally, the method is extended to compute NF of a CMOS translinear circuit biased in weak inversion.

• 社団法人電子情報通信学会の論文
• 2004-09-01

著者

• Sanchez-lopez Carlos

  Electronics Department With The Integrated-circuit Design Group At Inaoe-mexico

• TLELO-CUAUTLE Esteban

  Electronics Department with the Integrated-Circuit Design group at INAOE-MEXICO

関連論文

• Symbolic Computation of NF of Transistor Circuits(Nonlinear Problems)

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