A Low-Power Architecture for Extended Finite State Machines Using Input Gating(Logic Synthesis)(<Special Section>VLSI Design and CAD Algorithms)

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概要

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• In this paper, we investigate a low-power architecture for designs modeled as an Extended Finite State Machine (EFSM). It is based on the general dynamic power management concept[2], in which the redundant computation can be dynamically disabled to reduce the overall power dissipation. The contribution of this paper is mainly a systematic procedure to identify almost maximal amount of redundant computation in a design given as an EFSM. There are two levels of redundant computation to be exploited-one is based on the machine state information, while the other is based on the transition information. After the extraction of the redundant computation, a low-power architecture using input gating [10] is proposed to synthesize the final circuit. We tested the technique on a design computing a number's modulo inverse. Experimental results show that 31% power reduction can be achieved at the costs of 2% timing penalty and 16% area overhead.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• Huang Shi-yu

  Department Of Electrical Engineering National Tsing-hua University

• LIU Chien-Jyh

  Department of Electrical Engineering, National Tsing-Hua University

• Liu Chien-jyh

  Department Of Electrical Engineering National Tsing-hua University

関連論文

• A Low-Power Architecture for Extended Finite State Machines Using Input Gating(Logic Synthesis)(VLSI Design and CAD Algorithms)

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