SP2 : A Very Large-Scale Event Driven Logic Simulation Hardware(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

• 社団法人電子情報通信学会の論文
• 2002-12-01

著者

• Komatsu H

  Computer Business Group Fujitsu Ltd.

• HAMAMURA Hirofumi

  Corporate Production Engineering Group, Fujitsu Ltd.

• KOMATSU Hiroaki

  Computer Business Group, Fujitsu Ltd.

• Hamamura Hirofumi

  Corporate Production Engineering Group Fujitsu Ltd.

関連論文

• SP2 : A Very Large-Scale Event Driven Logic Simulation Hardware(Special Section on VLSI Design and CAD Algorithms)

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