CMOS Transistor in Nanoscale Era(Special Issue on Advanced Sub-0.1 μm CMOS Devices)

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概要

• 論文の詳細を見る

• This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.

• 一般社団法人電子情報通信学会の論文
• 2002-05-01

著者

• Yu Bin

  Amd Inc.

• YU Bin

  AMD, Inc.

関連論文

• CMOS Transistor in Nanoscale Era(Special Issue on Advanced Sub-0.1 μm CMOS Devices)

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