Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.

• 一般社団法人電子情報通信学会の論文
• 2001-08-01

著者

• Lee Seung-hoon

  The Author Is With Department Of Electronics Engineering Sogang University

• LEE Joon-Seok

  The author is with Hynix Co., Ltd.,

• JOO Se-Hoon

  The author is with Omnitel Co., Ltd.,

• Joo Se-hoon

  The Author Is With Omnitel Co. Ltd.

関連論文

• A Low-Ripple Switched-Capacitor DC-DC up Converter for Low-Voltage Applications
• Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC

スポンサーリンク