A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones (Special Issue on Low-Power High-Performance VLSI Processors and Technologies

概要

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We propose a vector-pipeline processor VPDSP for low-rate videophones which can encode and decode 10frames/sec. of QCIF through a 29.2kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35μm CMOS process. The area of the VP-DSP core is 4.26mm^2. It works properly at 25MHz/1.6V with a power consumption of 49mW. Its peak performance is up to 400MOPS, 8.2GOPS/W.
社団法人電子情報通信学会の論文
2001-02-01