A Jitter Suppression Technique for a Clock Multiplier

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概要

• 論文の詳細を見る

• This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5mUI rms and an extremely low jitter cutoff frequency of about 50kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.

• 2000-04-25

著者

• Ishii K

  Utsunomiya Univ. Utsunomiya‐shi Jpn

• Kishine Keiji

  The Authors Are With Ntt Network Innovation Laboratories

• Ichino Haruhiko

  The Authors Are With Ntt Network Innovation Laboratories

• ISHII Kiyoshi

  The authors are with NTT Network Innovation Laboratories

関連論文

• A Jitter Suppression Technique for a Clock Multiplier
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