A Low-Voltage 42.4G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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概要

• 論文の詳細を見る

• Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and / or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1k-bit read-bus and 1k-bit write-bus that each works concurrently, and has amplitude from 0V to 1V, hence the measured power consumption is only 0.3W at a frequency of 166MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4G-BPS bandwidth.

• 社団法人電子情報通信学会の論文
• 2000-02-25

著者

• Mori K

  System-lsi Division As-memory Group Mitsubishi Electric Corporation

• Inoue Kazunari

  System-lsi Division As-memory Group Mitsubishi Electric Corporation

• Mori Kaori

  System-lsi Division As-memory Group Mitsubishi Electric Corporation

• Fukagawa Shuji

  System-lsi Division As-memory Group Mitsubishi Electric Corporation

• Abe Hideaki

  System-lsi Division As-memory Group Mitsubishi Electric Corporation

関連論文

• A Low-Voltage 42.4G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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